1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly, to an internal voltage generator that generates an internal voltage for a Delay Locked Loop (DLL) and an internal clock generator including the same, and an internal voltage generating method for a DLL.
2. Discussion of Related Art
In general, semiconductor memory devices that operate in synchronization with a clock signal, such as synchronous semiconductor memory devices, include an internal clock generator that receives an external clock signal and generates an internal clock signal. The internal clock generator may be implemented in various manners. A DLL that can control a delay amount of the internal clock signal accurately is generally used for the internal clock generator.
Meanwhile, the DLL uses a DLL internal voltage which is generated by the DLL internal voltage generator as its operating voltage. For the purpose of an accurate operation of the DLL, it is important for the internal voltage generator to generate a stabilized DLL internal voltage.
FIG. 1 is a schematic block diagram of a DLL and a DLL internal voltage generator in the related art.
Referring to FIG. 1, the internal voltage generator 10 includes an active voltage generator 11 and a standby voltage generator 12. A DLL 20 uses an internal voltage VD1, which is generated by the active voltage generator 11 or the standby voltage generator 12, as an operating voltage.
The active voltage generator 11 operates only during an active period of a semiconductor memory device (for example, during a data access period of a semiconductor memory device) in response to an active signal ACT_FLG. Accordingly, the active voltage generator 11 strops its operation while the active signal ACT_FLG is disabled.
Meanwhile, the standby voltage generator 12 always operates without regard to the active period of the semiconductor memory device. In general, the standby voltage generator 12 is implemented using circuits with low current consumption in comparison with the active voltage generator 11 in order to save current consumption in the standby state.
In the case where the current consumption amount of the semiconductor memory device must be minimized as in a power-down mode or a self refresh mode, the standby voltage generator 12 functions to sustain the internal voltage VD1 to a set voltage (i.e., a reference voltage (VREF) level while consuming a minimum current.
In the active period in which variation in the amount of an internal power supply of the semiconductor memory device is great and a current consumption amount is high due to frequent operations of the DLL 20 (i.e., the access period of the semiconductor memory device in which the read or write operation is executed), however, the standby voltage generator 12 cannot sustain the internal voltage VD1 to the reference voltage (VREF) level. As a result, if only the standby voltage generator 12 operates in the active period, the internal voltage VD1 abruptly reduces. To prevent the problem, the internal voltage generator 10 includes the active voltage generator 11 that further generates the internal voltage VD1 in the active period in order to stabilize the internal voltage VD1.
Meanwhile, the semiconductor memory device enters the power-down mode during the period in which it does not actually operate in order to save current consumption. At this time, a time which is taken for the DLL internal voltage VD1 to restore to the reference voltage (VREF) level after the semiconductor memory device exits the power-down mode may be varied depending on the operating state of the semiconductor memory device immediately before entering the power-down mode. This will be described in more detail below.
For example, in the case where the semiconductor memory device enters from the active state to the power-down mode, the internal voltage generator 10 maintains its operating state immediately before the power-down mode when the semiconductor memory device exits the power-down mode. That is, since it is immediately before entering the power-down mode (i.e., the semiconductor memory device is in the active state (i.e., both the active voltage generator 11 and the standby voltage generator 12 operate)), both the active voltage generator 11 and the standby voltage generator 12 operate even after the semiconductor memory device exits the power-down mode. As a result, the internal voltage VD1 can be rapidly stabilized to the reference voltage (VREF) level.
In the case where the semiconductor memory device enters from a precharge state (i.e., a state where the read or write operation is not performed) to the power-down mode, a time which is taken for the internal voltage VD1 to be stabilized to the reference voltage (VREF) level is significantly longer than that of the case described above when the semiconductor memory device exits the power-down mode. This is because in the precharge state of the semiconductor memory device immediately before entering the power-down mode, only the standby voltage generator 12 operates in order to save current consumption, and only the standby voltage generator 12 operates even immediately after the semiconductor memory device exits the power-down mode.
The standby voltage generator 12 is implemented using circuits with less current consumption compared with the active voltage generator 11 as described above. Therefore, the standby voltage generator 12 has less ability to restore the internal voltage VD1 to the reference voltage (VREF) level in comparison with the active voltage generator 11. In other words, the response speed of the standby voltage generator 12 to variation in the internal voltage VD1 is slower than that of the active voltage generator 11.
Furthermore, the current driving ability of the standby voltage generator 12 is smaller than that of the active voltage generator 11. Accordingly, when the semiconductor memory device enters from the precharge state to the power-down mode rather than when the semiconductor memory device enters from the active state to the power-down mode, a time which is taken for the internal voltage VD1 to be stabilized to the reference voltage (VREF) level right after the power-down mode is longer.
On the other hand, the DLL 20 stops the operation of generating the internal clock signals DCK, DCKB in the power-down mode in order to save current consumption, and begins the operation of generating internal clock signals DCK, DCKB after exiting the power-down mode. As a result, when the DLL 20 begins operating right after the semiconductor memory device exits the power-down mode, current consumption of the DLL 20 is abruptly increased and the internal voltage VD1 is abruptly reduced (i.e., the internal voltage VD1 is fluctuated).
At this time, if only the standby voltage generator 12 operates, the internal voltage VD1 can restore to the reference voltage (VREF) level more rapidly. When the DLL 20 begins operating, the internal voltage VD1 is not restored to a given level rapidly. Accordingly, a problem arises because the DLL 20 cannot operate normally. This problem may become worse when the current consumption amount of the DLL 20 is the greatest (i.e., when the number of unit delay units that operate actually is the largest because the delay time of the DLL 20 is set to the greatest) right before the DLL 20 is disabled. This is because when the DLL 20 is enabled again, the DLL 20 operates at a delay time set in the previous operation. Accordingly, as the delay time set in the previous operation is increased, the level of the internal voltage VD1 when the DLL 20 is enabled is further decreased.
To prevent the problem, another example of the DLL internal voltage generator in which the level of an internal voltage VD2 is forcedly increased during a predetermined time when the DLL 20 is enabled is shown in FIG. 2.
Referring to FIG. 2, a PMOS transistor 40 operating as a pull-up circuit is connected to an output node NOUT of a DLL internal voltage generator 30. The PMOS transistor 40 supplies the output node NOUT with a power supply voltage VDD in response to a control signal EXTP which is disabled for a predetermined time when the DLL 20 is enabled. As a result, the level of the internal voltage VD2 output to the output node NOUT by the DLL internal voltage generator 30 is forcedly increased.
However, the PMOS transistor 40 increases the internal voltage VD2 without regard to a current level of the internal voltage VD2. Accordingly, there is a problem in which an overshoot phenomenon is generated due to an excessive increase of the internal voltage VD2. Accordingly, there is a problem in that the DLL internal voltage generator 10 cannot sustain the DLL internal voltage VD1 or VD2 more stably when the DLL 20 is enabled after being disabled.
If the internal voltage VD1 is not rapidly stabilized to the reference voltage (VREF) level immediately after the semiconductor memory device exits the power-down mode, the DLL 20 cannot generate stabilized internal clock signals DCK, DCKB stably. Accordingly, a problem arises because the read or write operation of the semiconductor memory device, which will be executed later, is not normally performed.